Pinnacles Component Information Standard (PCIS), Version 1.5-1-081099

Element: Definition List

Tag: <def.list>

Definition:
A list in which each item in the list consists of two parts, a term (a word or phrase) and some information about that term (usually a definition or explanation).

Remarks:
In the Definition List (def.list) element, the Definition List Term (<def.term>) element is the word or phrase being explained (such as a glossary term being defined or an error code being described) and the Definition (<def>) element contains the information about this term (the definition, explanation or other item). A Definition List (def.list) is usually a series of Definition List Items (<def.item>s), each of which contains a term and a definition.

A Definition List (def.list) may also be divided into a series of smaller lists, each of which has a heading. These sublists are called blocks; a Definition List Block of Items (<def.block>) contains a title and as many Definition List Items (<def.item>s) as needed.

The tag minimization parameter does not appear in the XML version of this element (because it is forbidden by XML).

Associated Attributes:

Descriptive Name Attribute Name Default Value

Division Class "div.class" IMPLIED

Unique Identifier "id" REQUIRED

Label "label" IMPLIED

Identifier of Language Used "lang.id" IMPLIED

Product IDs "pids" IMPLIED

Element Content:
This element can contain:

A Title (<title>) followed by

Definition List Term Heading (<term.heading>)

Definition List Definition Heading (<def.heading>)

Definition List Item (<def.item>)

Definition List Block of Items (<def.block>)

Pools:
This element is part of:

The General Paragraph-Level Elements pool (gen.para)

The List Elements pool (lists)

The All Paragraph-Level Elements pool (all.para)

SGML Model:

<!ELEMENT def.list - - (title?, (term.heading,def.heading?)?, ((def.item+,def.block*)|def.block+)) > <!ATTLIST def.list %common.atts; >

Formatted Example:

RAM
MAD31 is not used. MAD30:39 signals output an encoded address range select and are driven high or low.

I/O
Signals output an encoded address range selected.

DRAM
Signals contain data bits 29-31 when DRAM is in 32-bit configuration. When DRAM is in 16-bit configuration, these signals are unused and are floated.

DRAM write
During a DRAM write operation, only those bytes with a corresponding write enable signal asserted are driven by the 82961KA.

Tagged Example:

<DEF.LIST id="B57">
<DEF.ITEM id="B58"><DEF.TERM id="B59">RAM</DEF.TERM>
<DEF id="B60">MAD31 is not used. MAD30:39signals output an encoded address range select and are driven high or low.</DEF></DEF.ITEM>
<DEF.ITEM id="B62"><DEF.TERM id="B63">I/O</DEF.TERM>
<DEF id="B64">Signals output an encoded address range selected.</DEF></DEF.ITEM>
<DEF.ITEM id="B66"><DEF.TERM id="B67">DRAM</DEF.TERM>
<DEF id="B68">Signals contain data bits 29-31 when DRAM is in 32-bit configuration. When DRAM is in 16-bit configuration, these signals are unused and are floated.</DEF></DEF.ITEM></DEF.LIST>During a DRAM write operation, only those bytes with a corresponding write enable signal asserted are driven by the 82961KA.

Standard Version: 1.1
Original version: March 11, 1994
Last updated: PCIS 1.4 199712 pid.fragment attribute updated to pids; value of div.class updated to implied